Pin side edge mount connector and systems and methods thereof

ABSTRACT

A printed circuit board (PCB) device including one or more insulating layers and one or more conducting layers arranged to form a layer stack; and one or more blind holes disposed along a side edge of the layer stack and parallel to a plane of the layer stack. Each of the one or more blind holes along the side edge of the layer stack is configured to receive a pin. Each pin can make an electrical connection with a corresponding blind hole.

Embodiments of the disclosed subject matter relate to pin edge mountconnectors and systems and methods thereof.

SUMMARY

The present disclosure relates to a printed circuit board (PCB) deviceincluding: one or more insulating layers and one or more conductinglayers arranged to form a layer stack, a plane of the one or moreinsulating layers being parallel to a plane of the one or moreconducting layers; one or more conducting tracks; and one or more blindholes disposed in a side edge of the layer stack, each of the one ormore blind holes having a depth that extends from the side edge into thelayer stack in a direction parallel to the plane of the one or moreinsulating layers and the plane of the one or more conducting layers,the one or more blind holes being plated with a conducting material,wherein each of the one or more blind holes is configured to receive apin.

The present disclosure additionally relates to a printed circuit board(PCB) system including: one or more insulating layers and one or moreconducting layers arranged to form a layer stack; one or more blindholes disposed along a side edge of the layer stack and parallel to aplane of the layer stack; at least one pin; and a housing configured tohold the at least one pin and be removably mounted to the side edge ofthe layer stack, wherein each said at least one pin held by the housingis configured to be inserted into and retained by a respective one ofthe one or more blind holes.

The present disclosure additionally relates to a method, includingproviding one or more insulating layers and one or more conductinglayers arranged to form a layer stackup, a plane of the one or moreinsulating layers being parallel to a plane of the one or moreconducting layers; providing one or more conducting tracks toelectrically couple one or more blind holes to components on the layerstack; and providing one or more blind holes disposed in a side edge ofthe layer stack, each of the one or more blind holes having a depth thatextends from the side edge into the layer stack in a direction parallelto the plane of the one or more insulating layers and the plane of theone or more conducting layers, the one or more blind holes being platedwith a conducting material, wherein each of the one or more blind holesis configured to receive a pin.

The foregoing paragraphs have been provided by way of generalintroduction, and are not intended to limit the scope of the followingclaims. The described embodiments, together with further advantages,will be best understood by reference to the following detaileddescription taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the disclosure and many of the attendantadvantages thereof will be readily obtained as the same becomes betterunderstood by reference to the following detailed description whenconsidered in connection with the accompanying drawings, wherein:

FIGS. 1A and 1B show sectional views of a pin inserted into athrough-hole via of a printed circuit board (PCB) according to aconventional approach.

FIG. 2 is a perspective view of a PCB and an edge mount connector,according to an exemplary embodiment of the present disclosure.

FIG. 3 shows perspective views of an edge mount connector mountable on aPCB, according to an exemplary embodiment of the present disclosure.

FIG. 4A is a cross-sectional view of an edge mount connector mounted ona PCB, according to an exemplary embodiment of the present disclosure.

FIG. 4B is a cross-sectional view of an edge mount connector mounted ona PCB with multiple layers, according to an exemplary embodiment of thepresent disclosure.

FIG. 4C is a side-view schematic of multiple PCBs with mounted edgemount connectors stacked together, according to an exemplary embodimentof the present disclosure.

FIG. 5A is a perspective view of tracks in layers of the PCB, accordingto an exemplary embodiment of the present disclosure.

FIG. 5B is a perspective view of the tracks in the layers of the PCB,according to an exemplary embodiment of the present disclosure.

FIG. 6 is a flow chart of a method according to embodiments of thedisclosed subject matter.

DETAILED DESCRIPTION

The description set forth below in connection with the appended drawingsis intended as a description of various aspects of the disclosed subjectmatter and is not necessarily intended to represent the only aspect(s).In certain instances, the description includes specific details for thepurpose of providing an understanding of the disclosed subject matter.However, it will be apparent to those skilled in the art that aspectsmay be practiced without these specific details. In some instances,well-known structures and components may be shown in block diagram formin order to avoid obscuring the concepts of the disclosed subjectmatter.

Reference throughout the specification to “one aspect” or “an aspect”means that a particular feature, structure, characteristic, operation,or function described in connection with an aspect is included in atleast one aspect of the disclosed subject matter. Thus, any appearanceof the phrases “in one aspect” or “in an aspect” in the specification isnot necessarily referring to the same aspect. Further, the particularfeatures, structures, characteristics, operations, or functions may becombined in any suitable manner in one or more aspects. Further, it isintended that aspects of the disclosed subject matter can and do covermodifications and variations of the described aspects.

It must be noted that, as used in the specification and the appendedclaims, the singular forms “a,” “an,” and “the” include plural referentsunless the context clearly dictates otherwise. That is, unless clearlyspecified otherwise, as used herein the words “a” and “an” and the likecarry the meaning of “one or more.” Additionally, it is to be understoodthat terms such as “upper,” “lower,” “front,” “rear,” “side,”“interior,” “exterior,” and the like that may be used herein, merelydescribe points of reference and do not necessarily limit aspects of thedisclosed subject matter to any particular orientation or configuration.Furthermore, terms such as “first,” “second,” “third,” etc., merelyidentify one of a number of portions, components, points of reference,operations and/or functions as described herein, and likewise do notnecessarily limit aspects of the disclosed subject matter to anyparticular configuration or orientation.

A printed circuit board (PCB) may range in complexity from a singleplanar layer including tracks to connect components and vias on a singlesurface (i.e., a 1-layer PCB), to multi-layer stacks with track designsincluding tracks routed between layers to reach vias that may be buried,blind, or through-hole vias. Connectors holding pins may be attached tothe PCB such that the pins are inserted into the vias in a substantiallytransverse (e.g., perpendicular) orientation relative to the plane ofthe PCB layer(s). The transverse orientation of the inserted pins canyield a connector package that may sit on a top or bottom surface of thePCB itself.

FIG. 1A shows an example of the substantially transverse configuration.FIG. 1A illustrates a sectional perspective view of an exemplary pin105, but in the context of interfacing with a top surface 198 (or abottom surface 197 depending upon frame of reference) of a printedcircuit board (PCB) 120. FIG. 1B illustrates a sectional perspectiveview of the pin 105 installed orthogonal to the printed circuit board(PCB) 120. The PCB 120 may include a through-hole via 110 that is platedwith a plating 115 that is conductive. The pin 105 may be inserted intothe through-hole via 110 such that the pin 105 makes electrical contactwith the plating 115. The PCB 120 may include at least one conductivetrack (not shown) that electrically connects the through-hole via 110(by contacting the plating 115) to other components of the PCB 120. Theconductive track and plating 115 may be a material that is conductive,for example, copper, silver, graphene, or gold. The pin 105 may beconnected to a connector (not shown), which may include additional pins105 in an array. The connector may be displaced over a surface of thePCB 120 in order to hold all the pins 105. The connector maysubsequently be connected to another connector connected to another PCB120, such that the two connectors electrically couple the two PCBs 120.Optionally, the connector may instead be connected to other electricalcomponents.

The plated through-hole via 110 can carry current and pass through twoor more reference layers in a substantially transverse orientation(relative to the plane of the PCB), which may generate electromagnetic(EM) radiation that may be emitted from side edges of the PCB. Morespecifically, an EM wave may propagate radially away from the platedthrough-hole via 110 within the cavity between the two or more referencelayers, and upon reaching the PCB side edge, the two reference layersmay form a slot antenna and radiate noise. Such noise may causeelectromagnetic interference (EMI) to nearby equipment. Additionally,plated through-hole vias that include a stub portion may generateresonant frequency nulls that align with or near the Nyquist frequencyof the bit rate, which can result in high bit-error-ratio or linkfailure. For example, the through-hole via may extend through fivelayers of the PCB, but the track between the second and third layer ofthe five layers connects the through-hole via to another component inthe third layer. Thus, the stub portion may comprise the portion of thethrough-hole via in the third, fourth, and fifth layers that acts as anopen circuit.

The stub portion may also cause a quarter-wave resonance when asinusoidal signal is injected from a source into the pin at the top ofthe through-hole via and travels along the electrically connectiveportion until the signal reaches the junction of the track and the stubportion. Here, the sinusoidal signal may split, wherein some of thesignal travels along the track, and the remainder continues down thestub portion. Once the remainder reaches the other side of the stubportion, it may reflect towards the electrically connective portion. Andupon reaching the track junction, the remainder portion of the signalmay split again, with a portion traveling along the track and theremainder back to the source. If the time delay through the stub portionis equal to a quarter wavelength of the sinusoidal signal and thesinusoidal signal reflects at the stub portion, upon reaching the trackjunction again the sinusoidal signal will be delayed by a half of acycle and cancel most of the original signal.

In view of the foregoing, an improved configuration that can allow forparallel stacking of PCBs and/or for reducing EMI and resonance nulls isdesired. Embodiments of the disclosed subject matter involve platedblind holes disposed along a side edge of a PCB, particularly where theblind holes are configured to receive connector pins.

FIG. 2 illustrates a perspective partial view of a PCB 220 and an edgemount connector 225, according to an exemplary embodiment of the presentdisclosure. In an embodiment, the edge mount connector 225 may beconfigured to hold at least one pin 205, and the PCB 220 may include atleast one blind edge via 210. FIG. 2, for instance, shows a plurality ofpins 205, though the discussion herein may refer to the pins 205 insingular form as “pin 205” in reference to each of the pins 205.

The pin 205 may be attached (e.g., removably attached) to the edge mountconnector 225 and configured to be inserted into the at least one blindedge via 210. FIG. 2, for instance, shows a plurality of blind edge vias210, though the discussion herein may refer to the blind edge vias 210in singular form as “blind edge via 210” in reference to each of theblind edge vias 210. The blind edge via 210 may be plated with a plating215. As used herein, blind edge vias may be referred to as blind holes.

In an embodiment, the pin 205 may be, for example, a compliant pin andinclude a compliant portion 230. The compliant portion 230 may deformwhen abutting sidewall(s) of the blind edge via 210 (including theplating 215 plated therein). In this manner, the pin 205 may be insertedinto the blind edge via 210 even if a diameter of the blind edge via 210is narrower than a non-inserted diameter of the compliant portion 230.Such configuration of the pin 205 may increase tolerance to variabilityof sizing of the one blind edge via 210. Notably, the compliant portion230 may exert a predetermined force against the sidewall(s) of the blindedge via 210, which can lead to a reversible cold welding between thetwo structures.

The connection between the two structures can provide a reliablemechanical and electrical connection between the pin 205 and the plating215 of the blind edge via 210. Advantageously, using the pin 205 canprovide for solderless, internally powerful, gas-tight connections andcan allow for removal and replacement of the pin 205 as compared to apin that is soldered into the blind edge via 210. Additionally, thecompliant portion 230 of the pin 205 can allow the pin 205, and anystructure attached to the pin 205 (e.g., edge mount connector 225described below), to attach to the PCB 220 without the assistance of anadditional fastening device, for example, fastening screws, clasps,clips, and the like.

In an embodiment, the PCB 220 may be any circuit board used by those inthe art. For example, a single-sided, double-sided, or multi-layeredPCB. The PCB 220 may also be, for example, an integrated circuit (IC)such as an application-specific IC, or a hybrid circuit. The PCB 220 maybe fabricated from common substrate material for circuit boards, such asepoxy resin impregnated with woven glass fiber to form a planar panel.In a multi-layer PCB 220, multiple panels may be stacked in layers,alternating with layers of adhesive-backed foil, for example copperfoil, wherein the panels may be made insulating for some layers.

The PCB 220 may include a plurality of vias, such as through-hole vias,blind vias (e.g. blind edge via 210), and buried vias, where the viasmay be plated in order to electrically connect components in or onvarious layers of the PCB 220. Other than blind edge holes or vias asdefined herein (e.g., blind edge via 210), through-hole vias may beholes extending through the PCB 220, from the top surface 198 to theopposite bottom surface 197 of the PCB 220. Generally, according toembodiments of the disclosed subject matter, blind vias may be holesstarting at any exterior surface of the PCB 220 (or portions thereof,such as a single stack of a plurality of stacks of the PCB 220) andextending through a portion of the multi-layer stack. Buried vias, onthe other hand, may be holes formed by both starting and ending in aninterior layer of the multi-layer stack.

In an embodiment, the blind edge via 210 can be a substantiallycylindrical volume of material removed from the PCB 220 along a sideedge 299 of the PCB 220. As used herein, “side edge 299” may refer toedges of the PCB 220 other than the top surface 198 and the bottomsurface 197 and can include front, back, left and right side edges 299,whether free edges or mounted to a chassis or other fixture. That is tosay, the PCB 220 may have a thickness t (i.e., for the side edge 299)that is significantly less in dimension than a length L and a width W ofthe PCB 220. The surfaces formed along the length L and width W of thePCB 220 may be the top 198 and bottom surfaces 197 of the PCB 220.

A cross-sectional shape of the blind edge via 210 may be circular, andthe blind edge via 210 may be formed (e.g., drilled) into the side edge299 of the PCB 220. It should be noted that other shapes for the blindedge via 210 volume may be used, such as a square or oval cross-section.The blind edge via 210 may have a diameter and extend a predetermineddepth into the side edge 299 of the PCB 220. The blind edge via 210 maybe configured to receive the pin 205, as indicated above in discussingthe pin 205. Thus, the predetermined depth may be determined, forexample, based on a length of the pin 205 inserted therein.Alternatively, dimensions of the pin 205, such as length, diameter,etc., may be set based on corresponding characteristics of the blindedge via 210, such as depth, diameter, etc.

As previously mentioned, the blind edge via 210 may be plated with theplating 215 to provide a conductive surface for the pin 205 to contactwhen inserted. Thus, the blind edge via 210 (including the plating 215therein) may have a predetermined diameter (or width for a squarecross-section), wherein the predetermined diameter may be determined bya width of the compliant portion 230 of the pin 205. For example, thepredetermined diameter may be marginally narrower than the width of thecompliant portion 230 such that the compliant portion 230 is deformed(made narrower) upon insertion into the blind edge via 210 in order toform a reversible cold weld.

In an embodiment, the edge mount connector 225 may be an extendedstructure holding a plurality of the pins 205 (as shown). The PCB 220may include a plurality of the blind edge vias 210 along one or moreside edges 299 the PCB 220 (FIG. 2, for instance, shows blind edge vias210 along only one side edge 299). The plurality of pins 205 may bespaced along the edge mount connector 225 according to a spacing of theplurality of blind edge vias 210. Thus, the pins 205 may be aligned withthe blind edge vias 210 for mutual insertion (i.e., simultaneousinsertion) of the pins 205 into the respective blind edge vias 210. Theedge mount connector 225 may include a housing 235 having a height h.The height h of the housing 235 may be substantially equal to thethickness t of the PCB 220. Optionally, one or more edge mountconnectors 225 may be provided, one or more per each side edge 299 ofthe PCB 220.

FIG. 3 illustrates perspective “assembly” views of the edge mountconnector 225 mounted to the PCB 220, according to an exemplaryembodiment of the present disclosure. Generally speaking, the edge mountconnector 225 may be removably connected to the PCB 220, meaning thatthe edge mount connector 225 can be reliably held to the PCB 220 suchthat suitable mechanical connections can be established between the pinsand the blind edge vias 210 and removed from the PCB 220 with the pins205 remaining with the edge mount connector 225.

The edge mount connector 225 may be moved towards one of the side edges299 (e.g., left side edge 299) of the PCB 220 such that the plurality ofpins 205 are aligned and inserted into corresponding respective ones ofthe plurality of blind edge vias 210. For example, the edge mountconnector 225 may be pressed into the side edge of the PCB 220 such thatthe plurality of pins 205 are press-fit into the correspondingrespective ones of the plurality of blind edge vias 210. Notably, theedge mount connector 225 may not be provided on either the top surface198 or the bottom surface 197 of the PCB 220.

FIG. 4A illustrates a partial cross-sectional view of the edge mountconnector 225 mounted on the PCB 220, according to an exemplaryembodiment of the present disclosure. FIG. 4B illustrates across-sectional view of the edge mount connector 225 mounted on the PCB220 with multiple layers, according to an exemplary embodiment of thepresent disclosure. As previously mentioned, multiple panels of the PCB220 may be stacked together and alternating with layers of conductivefoil to form a layer stack, wherein the panels may be made insulatingfor some layers. This may result in the PCB 220 with the thickness t inFIG. 4B.

In an embodiment, the thickness t may be greater than the diameter ofthe at least one pin 205. The blind edge via 210 may be disposed betweenthe top surface 198 and bottom surface 197 of the PCB 220. In anembodiment, the thickness t may be greater than the diameter of theblind edge vias 210, and the predetermined locations of the blind edgevias 210 between the layers may be determined by which layers a user maydesire for the blind edge via 210 (and the pin 205 inserted therein) toelectrically contact.

In an embodiment, the pins 205 and the blind edge vias 210 may be keyed,wherein an arrangement of the pins 205 and the blind edge vias 210 maybe such that a predetermined arrangement of the pins 205 on the edgemount connector 225 may allow connection to a predetermined side edge299 with a corresponding arrangement of blind edge vias 210.Concomitantly, an incorrect arrangement of the pins 205 on anon-corresponding edge mount connector 225 may prevent thenon-corresponding edge mount connector 225 from mounting to anon-corresponding side edge 299 due to the pins 205 not coupling withthe blind edge vias 210 of the non-corresponding side edge 299. Forexample, the pins 205 may have a predetermined spacing that matches thespacing of the blind edge vias 210 and the non-corresponding edge mountconnector 225 mounted on non-corresponding side edge 299 may result inthe pins 205 misaligned with the blind edge vias 210. It may beappreciated that the blind edge vias 210 have the predetermined spacing.In another example, the pins 205 may have varying lengths and thepredetermined arrangement of pins 205 with varying lengths maycorrespond to an arrangement of blind edge vias 210 with correspondingvarying depths. In another example, the pins 205 may have varyingcross-sectional shapes and the predetermined arrangement of pins 205with varying cross-sectional shapes may correspond to an arrangement ofblind edge vias 210 with corresponding varying cross-sectional shapes.

FIG. 4C illustrates a side elevational view of multiple PCBs 220 withmounted edge mount connectors 225 stacked together to form a PCB 220stack, according to an exemplary embodiment of the present disclosure.Notably, the orientation of the edge mount connector 225 disposed alongthe side edge 299 of the PCB 220, when mounted, are not over the area ofthe top surface 198 and bottom surface 197 of the PCB 220, and can allowfor relatively more dense stacking of multiple PCBs 220 as compared to aconfiguration where the connector is disposed over the area of the topsurface 198 and bottom surface 197 of the PCB 220. It may be appreciatedthat the height h of the housing 235 may be designed to provide adequatespacing between each PCB 220 in order to allow for cooling and thermalexpansion, or to eliminate the spacing entirely. For example, the PCB220 may include an air-cooling system, wherein there may be spacingbetween the PCBs 220 for air to travel between and undergo thermalexchange with the PCBs 220. For example, the PCB 220 may include anintegrated water-cooling system, wherein the spacing between the PCBs220 may be eliminated for more dense stacking.

FIGS. 5A and 5B illustrate perspective views of exemplary electricalconnections in the layers of the PCB 220, according to an exemplaryembodiment of the present disclosure. In an embodiment, the PCB 220 mayinclude at least one track 230. The at least one track 230 may be aconducting electrical connection between components in and/or on the PCB220. That is to say, the at least one track 230 may start in an internallayer and terminate in another internal layer (or the same internallayer), start on the top surface 198 and terminate on the top surface198, start in an internal layer and terminate on the top surface 198 orbottom surface 197, or start on the top surface 198 or bottom surface197 and terminate in an internal layer. For example, the at least onetrack 230 may electrically couple the plating 215 in the blind edge via210 (and thus the pin 205 inserted therein) to a component on the topsurface 198 through a blind via (not shown) extending partially into thePCB 220.

Notably, for the scenario where the at least one track 230 may start inan internal layer and terminate in another internal layer (or the sameinternal layer), the position of the at least one blind edge via 210along the side edge 299 may allow for the at least one track 230 to onlytravel from the blind edge via 210 to the target electrical component inthe PCB 220 between two layers without traveling across other layers.The at least one track 230 may be fabricated from a conductive material,for example copper, gold, silver, graphene, or aluminum. A plurality ofthe tracks 230 may originate from a single component, for example one ofthe blind edge vias 210 may split into two of the tracks 230 at theconnection point.

FIG. 6 is a flow diagram for a method 600 according to an exemplaryembodiment of the present disclosure.

In step S601, the layer stack of the PCB 220 may be provided. In stepS603, the at least one track 230 in the PCB 220 may be provided. In stepS605, the one or more blind edge vias 210 may be provided. In step S607,the pins 205 may be provided. In step S609, the housing 235 of the edgemount connector 225 may be provided. In step S611, the pins 205 may beattached to the housing 235. In step S613, the housing 235 may beattached to the side edge 299 of the layer stack of the PCB 220. In stepS615, the housing 235 may be optionally removed from the side edge 299of the layer stack of the PCB 220.

Advantageously, multiple PCBs 220 and edge mount connectors 225 may beclosely stacked in a layered configuration (such that the planes of eachPCB 220 are substantially parallel to each other in the stack) due tothe side edge positioning of the plurality of the at least one blindedge via 210. This is also due to the compliant portion 230 of the pin205 securing the pin 205 and the edge mount connector 225 to the blindedge vias 210 without additional fastening devices. Since additionalfastening devices may not be needed, less manufacturing material can beused to form the edge mount connector 225, allowing for a more compactform factor that enables dense stacking. Moreover, the height h of theedge mount connector 225 may be determined based on a desired spacingbetween layers of PCBs 220 in the stacked configuration. The height hlarger than the thickness t may allow for space between PCB 220 layersfor cooling and thermal expansion. A height h being substantially equalto the thickness t may allow for denser packaging.

As previously mentioned, through-hole vias (i.e., vias formedsubstantially transverse to the plane of the PCB 220) may generateelectromagnetic radiation that can emit from the side edges of the PCB220 and cause interference. In another advantage, the at least one blindedge via 210 being positioned along the edge of the PCB 220 may notresult in electromagnetic radiation generation traveling between twoconductive layers of the multi-layer stack, and thus may not emit fromthe edges of the PCB 220 like a slot antenna.

As previously mentioned, forming through-hole vias in the PCB 220 mayresult in the stub portion when only a portion of the through-hole viais used to electrically connect the through-hole via to anothercomponent in or on the PCB 220. In another advantage, the at least oneblind edge via 210 may not include a stub portion from which thequarter-wavelength reflection occurs (and thus the half cycle cancellingsignal), thereby reducing or eliminating the signal degrading effects ofresonance nulls.

Implementations of the disclosed subject matter may also be as set forthin the following parentheticals.

(1) A printed circuit board (PCB) device, comprising: one or moreinsulating layers and one or more conducting layers arranged to form alayer stack, a plane of the one or more insulating layers being parallelto a plane of the one or more conducting layers; one or more conductingtracks; and one or more blind holes disposed in a side edge of the layerstack, each of the one or more blind holes having a depth that extendsfrom the side edge into the layer stack in a direction parallel to theplane of the one or more insulating layers and the plane of the one ormore conducting layers, the one or more blind holes being plated with aconducting material, wherein each of the one or more blind holes isconfigured to receive a pin.

(2) The device of (1), wherein the conducting tracks electrically couplethe one or more blind holes to components on the PCB.

(3) The device of either (1) or (2), wherein each of the one or moreconducting tracks starts and terminates in an interior layer of thelayer stack

(4) The device of any one of (1)-(3), further comprising: the pin havinga compliant portion, wherein the one or more blind holes has a diameterand a depth, the pin has a length, and the compliant portion of the pinhas a width, the length of the pin is no greater than the depth of theone or more blind holes, the diameter of the one or more blind holes isno greater than the width of the compliant portion of the pin, thecompliant portion is configured to deform when the pin is inserted intothe blind hole, and the compliant portion is configured to retain thepin in the blind hole when the pin is fully seated in the blind hole.

(5) The device of any one of (1)-(4), further comprising a housingconfigured to hold each said pin, the housing having a predeterminedheight, wherein the housing is configured to be removably mounted to theside edge of the layer stack such that each said pin held by the housingis inserted into and retained by a respective one of the one or moreblind holes and such that the housing extends from the side edgeparallel to the plane of the one or more insulating layers and the planeof the one or more conducting layers.

(6) The device of any one of (1)-(5), wherein each of the one or moreblind holes is configured to retain the pin via a press fit.

(7) The device of any one of (1)-(6), wherein the predetermined heightof the housing is substantially equal to a thickness of the layer stack.

(8) The device of any one of (1)-(7), further comprising a plurality ofthe PCBs, wherein the plurality of PCBs form a stack in a thicknessdirection of the PCBs, the stack of PCBs have a top surface and a bottomsurface opposite the top surface, and the housing is disposed along theside edge of each of the plurality of the PCBs and is not disposed overthe top or bottom surfaces of the stack of PCBs.

(9) A printed circuit board (PCB) system, comprising one or moreinsulating layers and one or more conducting layers arranged to form alayer stack; one or more blind holes disposed along a side edge of thelayer stack and parallel to a plane of the layer stack; at least onepin; and a housing configured to hold the at least one pin and beremovably mounted to the side edge of the layer stack, wherein each saidat least one pin held by the housing is configured to be inserted intoand retained by a respective one of the one or more blind holes.

(10) The system of (9), wherein the at least one pin includes acompliant portion, the one or more blind holes have a diameter and adepth, the at least one pin has a length, and the compliant portion ofthe at least one pin has a width, the length of the at least one pin isno greater than the depth of the one or more blind holes, the diameterof the one or more blind holes is no greater than the width of thecompliant portion of the at least one pin, the compliant portion isconfigured to deform when the pin is inserted into the blind hole, andthe compliant portion is configured to retain the pin in the blind holewhen the pin is fully seated in the blind hole.

(11) The system of either (9) or (10), wherein a height of the housingis substantially equal to a thickness of the layer stack.

(12) The device of any one of (9)-(11), further comprising a pluralityof the PCBs, wherein the plurality of PCBs form a stack in a thicknessdirection of the PCBs, the stack of PCBs have a top surface and a bottomsurface opposite the top surface, and the housing is disposed along theside edge of each of the plurality of the PCBs and is not disposed overthe top or bottom surfaces of the stack of PCBs.

(13) The device of any one of (9)-(12), further comprising: one or moreconducting tracks, wherein the conducting tracks electrically couple theone or more blind holes to components on the PCB.

(14) The device of any one of (9)-(13), wherein each of the one or moreconducting tracks starts and terminates in an interior layer of thelayer stack.

(15) A method, comprising: providing one or more insulating layers andone or more conducting layers arranged to form a layer stack, a plane ofthe one or more insulating layers being parallel to a plane of the oneor more conducting layers; providing one or more conducting tracks toelectrically couple one or more blind holes to components on the layerstack; and providing one or more blind holes disposed in a side edge ofthe layer stack, each of the one or more blind holes having a depth thatextends from the side edge into the layer stack in a direction parallelto the plane of the one or more insulating layers and the plane of theone or more conducting layers, the one or more blind holes being platedwith a conducting material, wherein each of the one or more blind holesis configured to receive a pin.

(16) The method of (15), further comprising: providing the pin having acompliant portion, wherein the one or more blind holes has a diameterand a depth, the pin has a length, and the compliant portion of the pinincludes a width, the length of the pin is no greater than the depth ofthe one or more blind holes, the diameter of the one or more blind holesis no greater than the width of the compliant portion of the pin, andsaid providing the pin includes the compliant portion deforming when thepin is inserted into the blind hole, and the compliant portion retainingthe pin in the blind hole when the pin is fully seated in the blindhole.

(17) The method of either (15) or (16), further comprising providing ahousing configured to hold each said pin, the housing having apredetermined height, wherein providing the housing includes the housingbeing configured to be removably mounted to the side edge of the layerstack such that each said pin held by the housing is inserted into andretained by a respective one of the one or more blind holes and suchthat the housing extends from the side edge parallel to the plane of theone or more insulating layers and the plane of the one or moreconducting layers.

(18) The method of any one of (15)-(17), wherein said providing thehousing includes the one or more blind holes retaining each said pin viaa press fit.

(19) The method of any one of (15)-(18), wherein the predeterminedheight of the housing is substantially equal to a thickness of the layerstack

(20) The method of any one of (15)-(19), further comprising separatingthe housing from the layer stack, wherein the layer stack includes aplurality of the blind holes and the pins, and the separating thehousing from the layer stack includes substantially simultaneousextraction of the plurality of pins from the blind holes.

Obviously, numerous modifications and variations are possible in lightof the above teachings. It is therefore to be understood that within thescope of the appended claims, the invention may be practiced otherwisethan as specifically described herein. For example, preferable resultsmay be achieved if the steps of the disclosed techniques were performedin a different sequence, if components in the disclosed systems werecombined in a different manner, or if the components were replaced orsupplemented by other components.

Thus, the foregoing discussion discloses and describes merely exemplaryembodiments of the present invention. As will be understood by thoseskilled in the art, the present invention may be embodied in otherspecific forms without departing from the spirit or essentialcharacteristics thereof. Accordingly, the disclosure of the presentinvention is intended to be illustrative, but not limiting of the scopeof the invention, as well as other claims. The disclosure, including anyreadily discernible variants of the teachings herein, defines, in part,the scope of the foregoing claim terminology such that no inventivesubject matter is dedicated to the public.

1. A printed circuit board (PCB) device, comprising: one or moreinsulating layers and one or more conducting layers arranged to form alayer stack, a plane of the one or more insulating layers being parallelto a plane of the one or more conducting layers; one or more conductingtracks; and one or more blind holes disposed in a side edge of the layerstack, each of the one or more blind holes having a depth that extendsfrom the side edge into the layer stack in a direction parallel to theplane of the one or more insulating layers and the plane of the one ormore conducting layers, the one or more blind holes being plated with aconducting material, wherein each of the one or more blind holes isconfigured to receive a pin.
 2. The device of claim 1, wherein theconducting tracks electrically couple the one or more blind holes tocomponents on the PCB.
 3. The device of claim 2, wherein each of the oneor more conducting tracks starts and terminates in an interior layer ofthe layer stack.
 4. The device of claim 1, further comprising: the pinhaving a compliant portion, wherein the one or more blind holes has adiameter and a depth, the pin has a length, and the compliant portion ofthe pin has a width, the length of the pin is no greater than the depthof the one or more blind holes, the diameter of the one or more blindholes is no greater than the width of the compliant portion of the pin,the compliant portion is configured to deform when the pin is insertedinto the blind hole, and the compliant portion is configured to retainthe pin in the blind hole when the pin is fully seated in the blindhole.
 5. The device of claim 4, further comprising a housing configuredto hold each said pin, the housing having a predetermined height,wherein the housing is configured to be removably mounted to the sideedge of the layer stack such that each said pin held by the housing isinserted into and retained by a respective one of the one or more blindholes and such that the housing extends from the side edge parallel tothe plane of the one or more insulating layers and the plane of the oneor more conducting layers.
 6. The device of claim 1, wherein each of theone or more blind holes is configured to retain the pin via a press fit.7. The device of claim 5, wherein the predetermined height of thehousing is substantially equal to a thickness of the layer stack.
 8. Thedevice of claim 5, further comprising a plurality of the PCBs, whereinthe plurality of PCBs form a stack in a thickness direction of the PCBs,the stack of PCBs have a top surface and a bottom surface opposite thetop surface, and the housing is disposed along the side edge of each ofthe plurality of the PCBs and is not disposed over the top or bottomsurfaces of the stack of PCBs.
 9. A printed circuit board (PCB) system,comprising: one or more insulating layers and one or more conductinglayers arranged to form a layer stack; one or more blind holes disposedalong a side edge of the layer stack and parallel to a plane of thelayer stack; at least one pin; and a housing configured to hold the atleast one pin and be removably mounted to the side edge of the layerstack, wherein each said at least one pin held by the housing isconfigured to be inserted into and retained by a respective one of theone or more blind holes.
 10. The system of claim 9, wherein the at leastone pin includes a compliant portion, the one or more blind holes have adiameter and a depth, the at least one pin has a length, and thecompliant portion of the at least one pin has a width, the length of theat least one pin is no greater than the depth of the one or more blindholes, the diameter of the one or more blind holes is no greater thanthe width of the compliant portion of the at least one pin, thecompliant portion is configured to deform when the pin is inserted intothe blind hole, and the compliant portion is configured to retain thepin in the blind hole when the pin is fully seated in the blind hole.11. The system of claim 9, wherein a height of the housing issubstantially equal to a thickness of the layer stack.
 12. The system ofclaim 9, further comprising a plurality of the PCBs, wherein theplurality of PCBs form a stack in a thickness direction of the PCBs, thestack of PCBs have a top surface and a bottom surface opposite the topsurface, and the housing is disposed along the side edge of each of theplurality of the PCBs and is not disposed over the top or bottomsurfaces of the stack of PCBs.
 13. The system of claim 9, furthercomprising: one or more conducting tracks, wherein the conducting trackselectrically couple the one or more blind holes to components on thePCB.
 14. The system of claim 13, wherein each of the one or moreconducting tracks starts and terminates in an interior layer of thelayer stack.
 15. A method comprising: providing one or more insulatinglayers and one or more conducting layers arranged to form a layer stack,a plane of the one or more insulating layers being parallel to a planeof the one or more conducting layers; providing one or more conductingtracks to electrically couple one or more blind holes to components onthe layer stack; and providing one or more blind holes disposed in aside edge of the layer stack, each of the one or more blind holes havinga depth that extends from the side edge into the layer stack in adirection parallel to the plane of the one or more insulating layers andthe plane of the one or more conducting layers, the one or more blindholes being plated with a conducting material, wherein each of the oneor more blind holes is configured to receive a pin.
 16. The method ofclaim 15, further comprising: providing the pin having a compliantportion, wherein the one or more blind holes has a diameter and a depth,the pin has a length, and the compliant portion of the pin includes awidth, the length of the pin is no greater than the depth of the one ormore blind holes, the diameter of the one or more blind holes is nogreater than the width of the compliant portion of the pin, and saidproviding the pin includes the compliant portion deforming when the pinis inserted into the blind hole, and the compliant portion retaining thepin in the blind hole when the pin is fully seated in the blind hole.17. The method of claim 16, further comprising providing a housingconfigured to hold each said pin, the housing having a predeterminedheight, wherein providing the housing includes the housing beingconfigured to be removably mounted to the side edge of the layer stacksuch that each said pin held by the housing is inserted into andretained by a respective one of the one or more blind holes and suchthat the housing extends from the side edge parallel to the plane of theone or more insulating layers and the plane of the one or moreconducting layers.
 18. The method of claim 17, wherein said providingthe housing includes the one or more blind holes retaining each said pinvia a press fit.
 19. The method of claim 17, wherein the predeterminedheight of the housing is substantially equal to a thickness of the layerstack.
 20. The method of claim 17, further comprising separating thehousing from the layer stack, wherein the layer stack includes aplurality of the blind holes and the pins, and the separating thehousing from the layer stack includes substantially simultaneousextraction of the plurality of pins from the blind holes.